Conference and Workshop Papers

Chronological order

Conference and workshop papers

Michael Gschwind. Optimizing Data Sharing and Address Translation for the Cell BE Heterogeneous Chip Multiprocessor. ICCD 2008. IEEE, August 2008.

Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Alper Buyuktosunoglu and Chen-Yong Cher. Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008 - The 35th International Symposium on Computer Architecture. ACM/IEEE, June 2008.

D. Scott Guthridge. A Scalable, High Performance InfiniBand-Attached SAN Volume Controller. HiperIO'08 - Second International Workshop on High Performance I/O Systems and Data Intensive Computing. IEEE, June 2008.

Valentina Salapura, Alan Gara, Michael Gschwind, James C. Sexton, Robert E. Walkup and Karthik Ganesan. Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events. ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and Software. ACM, April 2008.

Chun-Yung Sung. Post CMOS Nanoelectronics Research for the Next Generation Logic Switch. VLSI-TSA. The Industrial Technology Research Institute (ITRI) , April 2008.

Chen-Yong Cher and Michael Gschwind. Cell GC: Using the Cell Synergistic Processor as a Garbage Collection Coprocessor. VEE 2008 - The 2008 ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments. ACM, March 2008.

M. Aater Suleman, Moinuddin K. Qureshi and Yale N. Patt. Feedback Driven Threading: Power-Efficient and High-Performance Execution of Multi-threaded Workloads on CMP. Architectural Support for Programming Language and Operating Systems (ASPLOS 2008). ACM, March 2008.

Valentina Salapura, Matthias A. Blumrich and Alan Gara. Design and Implementation of the Blue Gene/P Snoop Filter. The 14th International Symposium on High-Performance Computer Architecture. IEEE, February 2008. [ download ]

David Zhang, Qiuyuan Li, Rodric Rabbah and Saman Amarasinghe. A Lightweight Streaming Layer for Multicore Execution. Workshop on Design, Architecture and Simulation of Chip Multi-Processors . November 2007.

Michael Gschwind. System Optimization of the Cell B.E. for Efficient and Flexible Programmability. Invited/Keynote Speech at First Workshop on General Purpose Processing on Graphics Processing Units. October 2007.

Michael Gschwind. Integrated Execution for Heterogeneous Architectures: A System View. Keynote Speech, Operating System support for Heterogeneous Multicore Architectures, in conjunction with PACT-2007. September 2007.

Rodric Rabbah. Beyond Gaming: Programming the PLAYSTATION3 Cell Architecture for Cost-Effective Parallel Processing. CODES+ISSS 2007 - International Conference on Hardware/Software Codesign and System Synthesis . September 2007.

Michael Gschwind. Integrated Execution for Heterogeneous Architectures:A System View . OSHMA-PACT - Operating System support for Heterogeneous Multicore Architectures at The Sixteenth International Conference on Parallel Architectures and Compilation Techniques. ACM/IEEE/IFIP, September 2007.

Paul A. Karger. Performance and Security Lessons Learned from Virtualizing the Alpha Processor. ISCA 2007 - The 34th International Symposium on Computer Architecture. ACM and IEEE, June 2007.

Alper Buyuktosunoglu and Ruhi Sarikaya. Predicting Program Behavior Based on Objective Function Minimization. 2007 IEEE International Symposium on Workload Characterization . June 2007.

Weirong Zhu, Vugranam C. Sreedhar, Ziang Hu and Guang Gao. Efficient Fine-Grain Synchronization on Many-Core Architecture Using Synchronization State Buffer. ISCA 2007 - Internation Symposium on Computer Architecture. ACM, June 2007.

Joseph Sharkey, Alper Buyuktosunoglu and Pradip Bose. Evaluating Design Tradeoffs in On-Chip Power Management for CMPs. International Symposium on Low Power Electronics and Design (ISLPED). May 2007.

Paul A. Karger, David C. Toll and Suzanne K. Mcintosh. Processor Requirements for a High Security Smart Card Operating System. e-Smart 2007. Eurosmart and Global Platform, April 2007.

Dan Tsafrir. The Context-Switch Overhead Inflicted by Hardware Interrupts (and the Enigma of Do-Nothing Loops). ACM ExpCS 2007 - Workshop on Experimental Computer Science. ACM/USENIX, March 2007.