The global clock signals are arguably the most important signals on high-speed digital Very Large Scale Integration (VLSI) chips, consuming as much as ten percent of the power, and determining the timing and speed of all calculations and communication. Resonant clocking techniques could potentially be used on most digital chips to recycle the clock energy from cycle to cycle, and to reduce performance-robbing clock jitter and skew.
Virtually all activity on most VLSI chips is controlled by the periodic “beat” of one or more global clock signals. Driving this signal to about 105 places on a high-end microprocessor CPU typically consumes about ten percent of the chip power. If the period or “beat” is not perfectly constant (clock jitter) or if the signal does not arrive everywhere at the desired time (clock skew) the chip will not run as fast as it could. Reducing chip power has also become more important for everything from portable devices to high-end servers. Usually most power-saving techniques involve a performance penalty, but resonant clocking has the promise of both recycling energy (reducing power) and actually increasing performance.
The global clock signal is perhaps more timing critical than any other signal on the chip, but it is also very repetitive and predictable. Resonant clocking techniques take advantage of this predictability to design a network that wants to oscillate at the desired frequency.
Resonant clock distributions have been designed and fabricated in the past, but usually at quite slow frequencies using off-chip discrete inductors, or for very small areas using on-chip inductors. To achieve high frequencies, and low skew across a large clock domain, it was necessary to innovate ways of designing distributed but tightly coupled oscillators. Many distributed oscillators are needed to resonate a large clock domain at high frequency, but unless these oscillators are tightly coupled, they could easily oscillate with different phases meaning unacceptable skew.
There are three basic types of resonant clock networks that have been published so far:
-Traveling wave oscillators (providing constant amplitude but varying phase)
-Standing wave oscillators (providing constant phase but varying amplitude)
-Coupled LC oscillators (providing constant phase and constant amplitude)
As noted only the third class of resonant clock network provides both constant phase and constant amplitude everywhere on the network, and this is the class we have chosen to pursue.
These coupled LC oscillators also allow a relatively small incremental change in design style from the present non-resonant clock distribution methodology presently used by IBM high-end processor chips. The present methodology involves large clock grids driven by a number of small wiring trees (see fig. 1). By simply adding four carefully designed spiral inductors and four capacitors to each tree, this non-resonant network becomes a resonant clock distribution network (fig. 2).
Figure 1: Large clock grids driven by a number of small wiring trees
Figure 2: Resonant clock distribution network
In figure 2, the hanging ends of the spiral inductors are connected to relatively large on-chip capacitors (not shown) that provide a local Vdd/2 voltage for the clock grid to oscillate around.
Research to date has included three test-chips with resonant clock structure. The first test-chip was an aggressive attempt to modify a small part of a clock distribution to be resonant at about three gigahertz. The chip including the resonant section worked up to 4.6 GHz, but on-chip diagnostics was not included. Two further chips designed at Columbia University using less aggressive technology at about one gigahertz had more testing capabilities and were shown to reduce both power and jitter by approximately a factor of three.
The research has been a collaboration between Steven Chan and his advisor Ken Shepard at Columbia University and Phillip Restle at IBM Research.
Related Publications
Steven C. Chan, Kenneth L. Shepard and Phillip J. Restle. Uniform-phase, Uniform-amplitude, Resonant Load Global Clock Distributions. IEEE Journal of Solid State Circuits 40(1):102-9, January 2005.
Steven C. Chan, Kenneth L. Shepard and Phillip J. Restle. 1.1 - 1.6GHz Distributed Differential Oscillator Global Clock Network. IEEE ISSCC Digest of Technical Papers. February 2005.
Steven C. Chan, Phillip J. Restle, Norman K. James and Robert L. Franch. A 4.6 GHz resonant global clock distribution network. IEEE ISSCC Digest of Technical Papers. February 2004.
Steven C. Chan, Kenneth L. Shepard and Phillip J. Restle. Design of Resonant Global Clock Distributions. Proceedings of the International Conference on Computer Design. 2003.
Phillip J. Restle, Albert E. Ruehli, Steven G. Walker and George Papadopoulos. Full-wave PEEC time-domain method for the modeling of on-chip interconnects. IEEE Trans. on Computer Aided Design 20(7):877-887, 2001.
Phillip J. Restle. Technical Visualizations in VLSI Design. Proceedings of the 38th Design Automation Conference. June 2001.
P. J. Restle, T. G. McNamara, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, M. J. Rohn, M. P. Quaranta, D. W. Boerstler, C. J. Alpert, C. A. Carter, R. N. Bailey, J. G. Petrovik, B. L. Krauter and and B. D. McCredie. A clock distribution network for microprocessors. 36(http://www.cisl.columbia.edu/courses/spring-2002/ee6930/papers/00918917.pdf):792-799, May 2001.
News and information
Clock technique resonates for nixing jitter
By R. Colin Johnson
EE Times
January 24, 2005
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Innovator's corner
Phillip Restle Researcher
What is the most exciting potential future use for the work you're doing?
While we are initially aiming at impacting high-end processors, resonant clocking could become extremely widespread in everything from nano-sensors to cell phones to supercomputers.
What is the most interesting part of your research?
When you cross discipline boundaries, like trying to integrate on-chip spiral inductors tightly with digital circuits, you can't predict where you are going to end up. The daily surprises, problems, interaction with colleagues, and occasional "eureka" solutions keep me motivated.
What inspired you to go into this field?
I have always enjoyed trying to understand the physical world by oscillating back and forth rapidly between theoretical and experimental activities (between thinking and doing). I've stayed here at IBM Research because we have the fortuitous combination of relative stability and challenges that are constantly changing.
What is your favorite invention of all time?
To stick with the theme of this page I'd say the pendulum, but to be more honest I'd say either board-sailing or computer games.
Research team
Related Research
Disciplines: Computer Science
, Electrical Engineering
Research Areas: VLSI Design