| Purdue University | ||||||
| Ongoing | Prof. Kaushik Roy | Ching-Te Kent Chuang | ||||
| Modeling and analysis of nanoscale CMOS devices/circuits,
Leakage and/or variation tolerant circuit techniques in nanoscale CMOS,
Exploration of new circuit topologies in double-gate device/technology | ||||||
| Purdue University | ||||||
| Ongoing | Prof. Jayathi Y. Murthy | Ching-Te Kent Chuang | ||||
| (1) Develop a thermal modeling methodology to incorporate Boltzmann Transport formulation into
Fluent thermal modeling tool to take into account the nano-scale effects such as phonon boundary
scattering and phonon confinement;
(2) Thermal modeling of scaled/future devices including UTSOI, Strained-Si devices, double-gate/FinFET,
carbon nanotube transistor, and 3D IC’s | ||||||