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IBM Journal of Research and Development  
Volume 34, Number 1, Page 12 (1990)
IBM RISC System/6000 processor
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The IBM RISC System/6000 processor: Hardware overview

by H. B. Bakoglu, G. F. Grohoski, R. K. Montoye
A highly concurrent superscalar second-generation family of RISC workstations and servers is described. The RISC System/6000® family is based on the new IBM POWER (Performance Optimization With Enhanced RISC) architecture; the hardware implementation takes advantage of this powerful RISC architecture and employs sophisticated design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio. The RS/6000 CPU features multiple-instruction dispatch, multiple functional units that operate concurrently, separate instruction and data caches, and zero-cycle branches. In this superscalar implementation, at a given cycle the equivalent of five operations can be executed simultaneously (a branch, a condition-register operation, and a floating-point multiple-add). The RS/6000 family supports the IBM Micro Channel architecture as well as high-speed serial optical links to provide a high-bandwidth I/O subsystem.
Related Subjects: Computer organization and design; Reduced-instruction-set computers (RISC); Computer architecture