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IBM Journal of Research and Development  
Volume 12, Number 4, Page 307 (1968)
Nontopical Issue
  Full article: arrowPDF   arrowCopyright info


A Balanced Capacitor Read-Only Storage

by S. A. Abbas, J. K. Ayling, C. E. Gifford, R. G. Gladu, T. C. Kwei, W. J. Taren
The design of a control storage system of 90 nsec access time and 200 nsec cycle time with permanently stored microinstructions is described. The storage medium used is the capacitive coupling between two groups of orthogonal conductors forming an information plane and a sense plane. There are 2816 words of 100 bits each, divided over two gates. The selection of an address line in the information plane is achieved through a transistor selection matrix. The output signal is sensed differentially at the mid-point of the sense line, which is matched at both ends. The sense amplifier output plus a "strobe" pulse set a latch for a portion of the cycle time and this provides the necessary inputs to the central processing unit. The major contributions to noise, such as sneak-path noise and select noise, are discussed and evaluated. The timing of the different pulses necessary to drive the array and the resulting outputs are explained and the marginal effects of time and amplitude variations are considered. Information can be changed off-line by replacing bit planes. Transcription of information in the bit planes is fully automated and can be speedily accomplished.
Related Subjects: Memory (computer) design and technology; Noise; Storage (computer) devices and systems