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IBM Journal of Research and Development  
Volume 38, Number 5, Page 537 (1994)
POWER2 and PowerPC architecture
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POWER2 instruction cache unit

by J. I. Barreh, R. T. Golla, L. B. Arimilli, P. J. Jordan
This paper describes the instruction cache unit (ICU) of the IBM POWER2™ processor, with emphasis on improvements over the original POWER ICU design. The POWER2 ICU incorporates a new compare-branch scheme that minimizes processing time penalties, a second branch processor, increased branch look-ahead capability, and doubled instruction-fetch and instruction- dispatch bandwidth.
Related Subjects: Computer architecture; Computer organization and design; Logic design and technology; Memory, cache; Reduced-instruction-set computers (RISC)