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IBM Journal of Research and Development  
Volume 38, Number 5, Page 563 (1994)
POWER2 and PowerPC architecture
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Exploiting functional parallelism of POWER2 to design high-performance numerical algorithms

by R. C. Agarwal, F. G. Gustavson, M. Zubair
We describe the algorithms and architecture approach to produce high-performance codes for numerically intensive computations. In this approach, for a given computation, we design algorithms so that they perform optimally when run on a target machine—in this case, the new POWER2™ machines from the RS/6000 family of RISC processors. The algorithmic features that we emphasize are functional parallelism, cache/register blocking, algorithmic prefetching, loop unrolling, and algorithmic restructuring. The architectural features of the POWER2 machine that we describe and that lead to high performance are multiple functional units, high bandwidth between registers, cache, and memory, a large number of fixed- and floating-point registers, and a large cache and TLB (translation lookaside buffer). The paper gives two examples that illustrate how the algorithms and architectural features interplay to produce high-performance codes. They are BLAS (basic linear algebra subroutines) and narrow-band matrix routin es. These routines are included in ESSL (Engineering and Scientific Subroutine Library); an overview of ESSL is also given in this paper.
Related Subjects: Algorithms; Computational methods; Mathematical functions and techniques; Mathematics (applied); Reduced-instruction-set computers (RISC)