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IBM Journal of Research and Development  
Volume 38, Number 5, Page 503 (1994)
POWER2 and PowerPC architecture
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POWER2 fixed-point, data cache, and storage control units

by D. J. Shippy, T. W. Griffith
The POWER2™ fixed-point, data cache, and storage control units provide a tightly integrated subunit for a second-generation high-performance superscalar RISC processor. These functional units provide dual fixed-point execution units and a large multiported data cache, as well as high-performance interfaces to memory, I/O, and the other execution units in the processor. These units provide the following features: dual fixed-point execution units, improved fixed-point/floating-point synchronization, new floating-point load and store quadword instructions, improved address translation, improved fixed-point multiply/divide, large multiported D-cache, increased bandwidth into and out of the caches through wider data buses, an improved external interrupt mechanism, and an improved I/O DMA mechanism to support multiple-streaming Micro Channels®.
Related Subjects: Arithmetic and logical unit design; Computer architecture; Computer organization and design; Logic design and technology; Reduced-instruction-set computers (RISC)