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Volume 39, Number 4, Page 383 (1995)
On-chip interconnection technology |
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Full article:
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VLSI on-chip interconnection performance simulations and measurements |
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by D. C. Edelstein, G. A. Sai-Halasz, Y.-J. Mii
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We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or “interconnects.” Performance can be affected by wiring geometry, materials, and processing details, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical properties, pulse propagation, and CPU cycle-time estimation, with particular attention to potential advantages of advanced materials and processes for wiring of high-performance CMOS microprocessors. Detailed performance improvements are presented for migration to copper wiring, low-ε dielectrics, and scaled-up interconnects on the final levels for long-line signal propagation. |
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| Related Subjects: CMOS; Integrated circuits; Interconnection technology; Materials technology; Measurement; Microprocessor systems and applications; Performance analysis; Semiconductor technology; Simulation; VLSI |
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