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IBM Journal of Research and Development  
Volume 38, Number 5, Page 577 (1994)
POWER2 and PowerPC architecture
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Instruction scheduling in the TOBEY compiler

by R. J. Blainey
The high performance of pipelined, superscalar processors such as the POWER2™ and PowerPC™ is achieved in large part through the parallel execution of instructions. This fine-grain parallelism cannot always be achieved by the processor alone, but relies to some extent on the ordering of the instructions in a program. This dependence implies that optimizing compilers for these processors must generate or schedule the instructions in an order that maximizes the possible parallelism. This paper describes the parts of the TOBEY compiler which address the instruction scheduling issue.
Related Subjects: Compilers and interpreters; Programming, programs, and programming languages; Reduced-instruction-set computers (RISC)