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IBM Journal of Research and Development  
Volume 34, Number 1, Page 23 (1990)
IBM RISC System/6000 processor
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IBM RISC System/6000 processor architecture

by R. R. Oehler, R. D. Groves
This paper describes the hardware architecture of the IBM RISC System/6000® processor, which combines basic RISC principles with a partitioning of registers by function into multiple ALUs. This allows a high degree of parallelism in execution and permits a compiler to generate highly optimized code to manage the interaction among parallel functions. Floating-point arithmetic is integrated into the architecture, and floating-point performance is comparable to that of many vector processors.
Related Subjects: Computer-aided design; Reduced-instruction-set computers (RISC); Computer architecture