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IBM Journal of Research and Development  
Volume 38, Number 5, Page 525 (1994)
POWER2 and PowerPC architecture
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POWER2 floating-point unit: Architecture and implementation

by T. N. Hicks, R. E. Fry, P. E. Harvey
The POWER2™ floating-point unit (FPU) extends the concept of the innovative multiply-add fused (MAF) ALU of the RISC System/6000® processor to provide a floating-point unit that sets new standards, not only for computation capability but for data throughput and processor flexibility. The POWER2 FPU achieves a performance (MFLOPS) rate never accomplished before by a personal workstation machine by 1) integrating dual generic MAF ALUs, 2) doubling the instruction bandwidth and quadrupling the data bandwidth over that of the POWER FPU, 3) adding support for additional functions, and 4) using dynamic instruction scheduling techniques to maximize instruction-level parallelism not only among its own internal units but with the rest of the CPU.
Related Subjects: Arithmetic and logical unit design; Computer architecture; Computer organization and design; Logic design and technology; Reduced-instruction-set computers (RISC)