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IBM Journal of Research and Development  
Volume 34, Number 1, Page 85 (1990)
IBM RISC System/6000 processor
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Instruction scheduling for the IBM RISC System/6000 processor

by H. S. Warren,Jr.
For fast execution on the IBM RISC System/6000® processor, instructions should be arranged in an order that uses the arithmetic units as efficiently as possible. This paper describes the scheduling requirements of the machine, and a scheduling algorithm for it that is used in two compilers.
Related Subjects: Memory (computer) management; Reduced-instruction-set computers (RISC); Schedulers