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IBM Journal of Research and Development  
Volume 40, Number 4, Page 431 (1996)
IBM ASIC design and testing
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Design planning for high-performance ASICs

by J. Y. Sayah, R. Gupta, D. D. Sherlekar, P. S. Honsinger, J. M. Apte, S. W. Bollinger, H. H. Chen, S. DasGupta, E. P. Hsieh, A. D. Huber, E. J. Hughes, Z. M. Kurzum, V. B. Rao, T. Tabtieng, V. Valijan, D. Y. Yang
Design planning is emerging as a solution to some of the most difficult challenges of the deep-submicron VLSI design era. Reducing design turnaround time for extremely large designs with ever-increasing clock speeds, while ensuring first-pass implementation success, is exhausting the capabilities of traditional design tools. To solve this problem, we have designed and implemented a hierarchical design planning system that consists of a tightly integrated set of design and analysis tools. The integrated run-time environment, with its rich set of hierarchical, timing-driven design planning and implementation functions, provides an advanced platform for realizing a variety of ASIC and custom methodologies. One of the system's particular strengths is its tight integration with an incremental, static timing engine that assists in achieving timing closure in high-performance designs. The design planner is in production use at IBM internal and at external ASIC design centers.
Related Subjects: ASICs; CMOS; Computer-aided design; Design automation; Design verification; Integrated circuit design; Logic synthesis; LSI design automation; Microelectronics; Testing, circuit; VLSI