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IBM Journal of Research and Development  
Volume 34, Number 1, Page 71 (1990)
IBM RISC System/6000 processor
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Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit

by E. Hokenek, R. K. Montoye
This paper presents a novel technique used in the multiply-add-fused (MAF) unit of the IBM RISC System/6000® (RS/6000) processor for normalizing the floating-point results. Unlike the conventional procedures applied thus far, the so-called leading-zero anticipator (LZA) of the RS/6000 carries out processing of the leading zeros and ones in parallel with floating-point addition. Therefore, the new circuitry reduces the total latency of the MAF unit by enabling the normalization and addition to take place in a single cycle.
Related Subjects: Computer organization and design; Reduced-instruction-set computers (RISC)