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IBM Journal of Research and Development  
Volume 34, Number 1, Page 93 (1990)
IBM RISC System/6000 processor
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Instruction scheduling beyond basic blocks

by M. C. Golumbic, V. Rainish
Instruction scheduling consists of the rearrangement or transformation of program statements, usually at the intermediate language or assembly code level, in order to reduce possible run-time delays between instructions. Such transformations must preserve data dependency and are subject to other constraints. Highly optimizing compilers employing instruction-scheduling techniques have proven to be effective in improving the performance of pipeline processors. Considerable attention has been given to scheduling code within the scope of basic blocks, i.e., straight-line sections of code. In this paper we present techniques for scheduling beyond basic blocks. This allows a further reduction in run-time delays such as those due, e.g., to branches and loops, enabling the exploiting of pipeline architectures which would not otherwise be possible.
Related Subjects: Memory (computer) management; Reduced-instruction-set computers (RISC); Schedulers