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Issues and strategies for the physical design of system-on-a-chip ASICs |
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by T. R. Bednar, P. H. Buffet, R. J. Darden, S. W. Gould, P. S. Zuchowski
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The density and performance of advanced silicon technologies have made system-on-a-chip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes. |
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| Related Subjects: ASICs; System-on-a-chip (SoC) |
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