IBM Journal of Research and Development
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IBM Journal of Research and Development

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Related Papers
2007IBM POWER6 accelerators: VMX and DFU
2007IBM POWER6 microprocessor physical design and design methodology
2007Power-constrained high-frequency circuits for the IBM POWER6 microprocessor
2006Optimizing CMOS technology for maximum performance
2006Ultralow-voltage, minimum-energy CMOS
2005Logic-based eDRAM: Origins and rationale for use
2005Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements
2004On-demand design service innovations
2003A direct-conversion receiver integrated circuit for WCDMA mobile systems
2003SiGe BiCMOS integrated circuits for high-speed serial communication links
2002Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
2002CMOS design near the limit of scaling
2002CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics
2002Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology
2002Infrastructure requirements for a large-scale, multi-site VLSI development project
2002Maintaining the benefits of CMOS scaling when scaling bogs down
2002New insights into carrier transport in n-MOSFETs
2002Power-constrained CMOS scaling limits
2002POWER4 system microarchitecture
2002Reliability limits for the gate insulator in CMOS technology
2002SOI technology for the GHz era
2002The circuit and physical design of the POWER4 microprocessor
2002Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?
2000Custom circuit design as a driver of microprocessor performance
1998A decompression core for PowerPC
1998A JBIG-ABIC compression engine for digital document processing
1997A high-frequency custom CMOS S/390 microprocessor
1997Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor
1997CMOS floating-point unit for the S/390 Parallel Enterprise Server G4
1997Standard-cell-based design methodology for high-performance support chips
1996BooleDozer: Logic synthesis for ASICs
1996Charge-metering sampling circuits and their applications
1996Circuit placement, chip optimization, and wire routing for IBM IC technology
1996Critical charge calculations for a bipolar SRAM array
1996Design methodology for IBM ASIC products
1996Design planning for high-performance ASICs
1996IC technology and ASIC design for the Cray J90 supercomputer
1996Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview
1996PowerPC AS A10 64-bit RISC microprocessor
1996Soft-error Monte Carlo modeling program, SEMM
1996Technology-migratable ASIC library design
1996Test methodologies and design automation for IBM ASICs
1995A 64Kb × 32 DRAM for graphics applications
1995A low-noise TTL-compatible CMOS off-chip driver circuit
1995CMOS circuits for Gb/s serial data communication
1995CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications
1995CMOS scaling into the 21st century: 0.1 μm and beyond
1995Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications
1995Design at the system level with VLSI CMOS
1995Digital delay line clock shapers and multipliers
1995Modeling and characterization of long on-chip interconnections for high-performance microprocessors
1995Multipurpose DRAM architecture for optimal power, performance, and product flexibility
1995Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier
1995Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor
1995The evolution of IBM CMOS DRAM technology
1992A single-chip IBM System/390 floating-point processor in CMOS
1992Directory and Trace memory chip with active discharge cell
1992Improved performance of IBM Enterprise System/9000 bipolar logic chips
1991A 128Kb CMOS static random-access memory
1991Visualization in a VLSI design automation system
1991Waveform-relaxation-based circuit simulation on the Victor V256 parallel processor
1989Architecture, design, and operating characteristics of a 12-ns CMOS functional cache chip
1987Shaping geometric objects by cumulative translational sweeps
1987Voronoi diagram for multiply-connected polygonal domains II: Implementation and application
1983Modeling of Integrated Circuit Defect Sensitivities
1983OYSTER: A Study of Integrated Circuits as Three-Dimensional Structures
1982A Conduction-Cooled Module for High-Performance LSI Devices
1982Bipolar Chip Design for a VLSI Microprocessor
1982Conduction Cooling for an LSI Package: A One-Dimensional Approach
1982Cost/Performance Single-Chip Module
1982Lead Reduction Among Combinatorial Logic Circuits
1982Model for Transient and Permanent Error-Detection and Fault-Isolation Coverage
1982Physical Design of a Custom 16-Bit Microprocessor
1981A 1024-Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell
1981A High-Density Bipolar Logic Masterslice for Small Systems
1981Bipolar Circuit Design for a 5000-Circuit VLSI Gate Array
1981Coupled Lossy Transmission Line Characterization and Simulation
1981Delay Regulation—A Circuit Solution to the Power/Performance Tradeof
1981Design Automation in IBM
1981Electronic Packaging Evolution in IBM
1981Semiconductor Logic Technology in IBM
1981Solid State Memory Development in IBM
1981Wire Length Distribution for Placements of Computer Logic