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2005	Logic-based eDRAM: Origins and rationale for use
2005	Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements
2004	On-demand design service innovations
2003	A direct-conversion receiver integrated circuit for WCDMA mobile systems
2003	SiGe BiCMOS integrated circuits for high-speed serial communication links
2002	Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
2002	CMOS design near the limit of scaling
2002	CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics
2002	Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology
2002	Infrastructure requirements for a large-scale, multi-site VLSI development project
2002	Maintaining the benefits of CMOS scaling when scaling bogs down
2002	New insights into carrier transport in n-MOSFETs
2002	Power-constrained CMOS scaling limits
2002	POWER4 system microarchitecture
2002	Reliability limits for the gate insulator in CMOS technology
2002	SOI technology for the GHz era
2002	The circuit and physical design of the POWER4 microprocessor
2002	Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?
2000	Custom circuit design as a driver of microprocessor performance
1998	A decompression core for PowerPC
1998	A JBIG-ABIC compression engine for digital document processing
1997	A high-frequency custom CMOS S/390 microprocessor
1997	Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor
1997	CMOS floating-point unit for the S/390 Parallel Enterprise Server G4
1997	Standard-cell-based design methodology for high-performance support chips
1996	BooleDozer: Logic synthesis for ASICs
1996	Charge-metering sampling circuits and their applications
1996	Circuit placement, chip optimization, and wire routing for IBM IC technology
1996	Critical charge calculations for a bipolar SRAM array
1996	Design methodology for IBM ASIC products
1996	Design planning for high-performance ASICs
1996	IC technology and ASIC design for the Cray J90 supercomputer
1996	Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview
1996	PowerPC AS A10 64-bit RISC microprocessor
1996	Soft-error Monte Carlo modeling program, SEMM
1996	Technology-migratable ASIC library design
1996	Test methodologies and design automation for IBM ASICs
1995	A 64Kb × 32 DRAM for graphics applications
1995	A low-noise TTL-compatible CMOS off-chip driver circuit
1995	CMOS circuits for Gb/s serial data communication
1995	CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications
1995	CMOS scaling into the 21st century: 0.1 μm and beyond
1995	Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications
1995	Design at the system level with VLSI CMOS
1995	Digital delay line clock shapers and multipliers
1995	Modeling and characterization of long on-chip interconnections for high-performance microprocessors
1995	Multipurpose DRAM architecture for optimal power, performance, and product flexibility
1995	Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier
1995	Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor
1995	The evolution of IBM CMOS DRAM technology
1992	A single-chip IBM System/390 floating-point processor in CMOS
1992	Directory and Trace memory chip with active discharge cell
1992	Improved performance of IBM Enterprise System/9000 bipolar logic chips
1991	A 128Kb CMOS static random-access memory
1991	Visualization in a VLSI design automation system
1991	Waveform-relaxation-based circuit simulation on the Victor V256 parallel processor
1989	Architecture, design, and operating characteristics of a 12-ns CMOS functional cache chip
1987	Shaping geometric objects by cumulative translational sweeps
1987	Voronoi diagram for multiply-connected polygonal domains II: Implementation and application
1983	Modeling of Integrated Circuit Defect Sensitivities
1983	OYSTER: A Study of Integrated Circuits as Three-Dimensional Structures
1982	A Conduction-Cooled Module for High-Performance LSI Devices
1982	Bipolar Chip Design for a VLSI Microprocessor
1982	Conduction Cooling for an LSI Package: A One-Dimensional Approach
1982	Cost/Performance Single-Chip Module
1982	Lead Reduction Among Combinatorial Logic Circuits
1982	Model for Transient and Permanent Error-Detection and Fault-Isolation Coverage
1982	Physical Design of a Custom 16-Bit Microprocessor
1981	A 1024-Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell
1981	A High-Density Bipolar Logic Masterslice for Small Systems
1981	Bipolar Circuit Design for a 5000-Circuit VLSI Gate Array
1981	Coupled Lossy Transmission Line Characterization and Simulation
1981	Delay Regulation—A Circuit Solution to the Power/Performance Tradeof
1981	Design Automation in IBM
1981	Electronic Packaging Evolution in IBM
1981	Semiconductor Logic Technology in IBM
1981	Solid State Memory Development in IBM
1981	Wire Length Distribution for Placements of Computer Logic