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Volume 52, Number 3, Page 293 (2008)
Soft Errors in Circuits and Systems |
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Phaser: Phased methodology for modeling the system-level effects of soft errors |
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by J. A. Rivers, P. Bose, P. Kudva, J.-D. Wellman, P. N. Sanda, E. H. Cannon, L. C. Alves
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This paper presents an overview of Phaser, a toolset and methodology for modeling the effects of soft errors on the architectural and microarchitectural functionality of a system. The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its design evolves through the phases of preconcept, concept, high-level design, and register-transfer-level design implementation. Phaser represents a strategic research vision that is being proposed as a next-generation toolset for predicting chip-level failure rates and studying reliability–performance tradeoffs during the phased design process. This paper primarily presents Phaser/M1, the early stage of the predictive modeling of behavior. |
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