|
|
 |
|
 |
Volume 51, Number 6, Page 685 (2007)
IBM POWER6 Microprocessor Technology |
|
Full article:
 HTML
PDF
| |
|
Copyright info |
|
|
|
|
|
| |
|
IBM POWER6 microprocessor physical design and design methodology |
|
by R. Berridge, R. M. AverillIII, A. E. Barish, M. A. Bowen, P. J. Camporese, J. DiLullo, P. E. Dudley, J. Keinert, D. W. Lewis, R. D. Morel, T. Rosser, N. S. Schwartz, P. Shephard, H. H. Smith, D. Thomas, P. J. Restle, J. R. Ripley, S. L. Runyon, P. M. Williams
|
|
|
|
 |
|
The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met. |
|
|
| Related Subjects: Clocking; IBM POWER6; Integrated circuit design; Logic design and technology |
|
|
|
