by S. P. Gaur, P. A. Habitz, Y.-J. Park, R. K. Cook, Y.-S. Huang, L. F. Wagner
Mathematical details of a two-dimensional semiconductor device simulation program are presented. Applicability of the carrier transport model to shallow junction bipolar transistors is discussed. Use of this program to optimize device structures in new bipolar technology is illustrated by presenting calculated device characteristics for variations in a few selected process conditions. Software links that automatically transfer data from a two-dimensional process simulation program and to a quasi-three-dimensional device equivalent circuit model generation program are also discussed.
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