Basic Design of a Josephson Technology Cache Memory
by S. M. Faris, W. H. Henkels, E. A. Valsamakis, H. H. Zappe
Design work on components for Josephson computer technology nondestructive read out cache memories has been published previously. In this paper, presenting a design for a 2.5-μm technology, 4 × 1K-bit cache chip with a nominal access time of about 500 ps as a basis, we show for the first time how these components are structured and interfaced. The cell, drivers, decoder, and a sense bus are based on designs which were experimentally verified in a 5-μm technology for which excellent agreement was found between computer simulations and measurements.