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IBM Journal of Research and Development  
Volume 28, Number 5, Page 625 (1984)
Design Automation
  Full article: arrowPDF   arrowCopyright info


A CMOS LSSD test generation system

by D. Leet, P. Shearon, R. France
Automatic test pattern generators based on the stuck-fault concept are theoretically inadequate in their ability to generate test patterns for CMOS circuits. A new set of pin faults, called CMOS faults, is discussed that can represent the necessary test pattern sequences for these circuits. Processing of these faults by a new test pattern generator, called the Enhanced Test Generator (ETG), is also described.
Related Subjects: Design automation; LSSD design and testing