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IBM Journal of Research and Development  
Volume 26, Number 3, Page 342 (1982)
Computer Packaging
  Full article: arrowPDF   arrowCopyright info


Lead Reduction Among Combinatorial Logic Circuits

by W. V. Vilkelis
The paper provides a description of the behavior of lead reduction among combinatorial logic circuits. Methods by which one may design the lead reduction architecture for modular packaging schemes are developed. The methods are then applied to the design of the lead reduction architecture of an integrated circuit chip and a nine-chip cell.
Related Subjects: Fabrication; Integrated circuit design; Logic design and technology