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IBM Journal of Research and Development  
Volume 27, Number 2, Page 140 (1983)
Constrained Channel Coding
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A ''Zero-Time'' VLSI Sorter

by G. Miranker, L. Tang, C.-K. Wong
A hardware sorter suitable for VLSI implementation is proposed. It operates in a parallel and pipelined fashion, with the actual sorting time absorbed by the input/output time. A detailed VLSI implementation is described which has a very favorable device count compared to existing static RAM.
Related Subjects: Algorithms; LSI; VLSI