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IBM Journal of Research and Development  
Volume 25, Number 2/3, Page 156 (1981)
VLSI Circuit Design
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High-Speed Binary Adder

by H. Ling
Based on the bit pair (ai bi) truth table, the carry propagate pi  and carry generate gi have dominated the carry-look-ahead formation process for more than two decades. This paper presents a new scheme in which the new carry propagation is examined by including the neighboring pairs (ai, biai+1bi+1). This schem e not only reduces the component count in design, but also requires fewer logic levels in adder implementation. In addition, this new algorithm offers an astonishingly uniform loading in fan-in and fan-out nesting.
Related Subjects: Arithmetic and logical unit design; Mathematics (applied)