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IBM Journal of Research and Development  
Volume 29, Number 6, Page 588 (1985)
Nontopical Issue
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Analysis of the holding current in CMOS latch-up

by H. Matino
The holding current in CMOS latch-up with or without well and/or substrate bias has been examined. Measurements indicate that the holding current increases significantly with reverse bias and low shunting base resistance. It is shown that a previous equation for the holding current is inaccurate, and a new equation for holding current with bias is presented.
Related Subjects: Semiconductor devices