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IBM Journal of Research and Development  
Volume 19, Number 4, Page 379 (1975)
Nontopical Issue
  Full article: arrowPDF   arrowCopyright info


High-Speed Dynamic Programmable Logic Array Chip

by R. A. Wood
This paper describes the circuit design of a programmable logic array chip using four-phase dynamic circuits, operating at a nominal cycle time of 230 nanoseconds. Bootstrap circuit techniques are used to obtain high function and performance by satisfying some special requirements of PLA designs. These include a simple means for two-bit partitioning of the data inputs, a noninverting buffer circuit between precharged arrays, and a fast, compact on-chip driver for heavily loaded arrays. Multiphase clocking enables the use of master/slave type JK flip-flops with minimum circuitry and power dissipation. A polarity hold function is provided at the outputs to allow interfacing the dynamic design to static output circuits.
Related Subjects: Arrays; Logic; Physics, solid state; Semiconductor devices